Pulse-based feature extraction for hardware-efficient neural recording systems

Current brain-machine interfaces have two machine learners-one for spike sorting and the second for intention decoding that acts on the sorted spatio-temporal spike train. In this paper, we propose a pulse-based feature extractor that can enable these two machine learners to be combined into one. We show from simulations and measurements that the information about the spike shape is still retained in the pulse counts-hence, the circuit can also be used as a traditional feature extractor. The proposed circuit also has the advantage of sharing several blocks with spike detector designs reducing system level cost. Fabricated in 65nm CMOS and operating from Vdd = 1V, the feature extractor dissipates roughly 2μW of power for an input spike rate of 100Hz.