A novel scheme for designing error correcting codes using cellular automata

This paper introduces a novel scheme of designing a new class of Error-Correcting Codes (ECC) using a simple structure built around additive cellular automata (CA) [1,2,3]. The regularity and cascadability of the three neighbourhood CA structure makes it an ideal choice for VLSI implementation. A scheme for the construction of Single-Error-Correcting (SEC) and Double- Error Detecting (DED) ccde is proposed which can be easily extended for information bits of any arbitrary length. Further, the basic scheme can be modified to generate code with arbitrary distance t. When compared to existing schemes, the method can be found to be much more. efficient in respect of silicon area overhead.