A fast fault simulator for sequential logic circuits

The P-model approach of modelling a combinational digital circuit using Petri nets has been introduced in [1]. Based on the P-model representation, the present paper introduces an efficient fault simula tor design for synchronous sequential circuits. The method consists in partitioning a given circuit into disjoint fanout-free regions (FFRs), translating each FFR into P-model, applying minimizing transforma tions, and performing fault simulation on the minimized FFRs. This technique is expected to be faster as compared to existing fault simu lation techniques.