Novel low power 10T SRAM cell on 90nm CMOS

For SRAM power, stability, delay and area are the major concerns. And they are trade-offs to each other. But all are important and should be in acceptable range. In this paper we mainly concentrated on power and stability and we designed a new 10T-SRAM for low power consumption. We placed two NMOS transistors for reducing power consumption. One transistor between supply voltage VDD and the latches formed by cross coupled inverters. This NMOS transistor is in diode connected mode and it scales down the VDD. As power is directly proportional to square of VDD total power is reduced by 98%. Another NMOS transistor is placed between latches and ground. This transistor is controlled with a control signal and used to reduce static power by 77%. But stability decreases when supply voltage decreases. In order to increase stability an extra PMOS transistor is placed in between access transistor and pull down transistor on both sides. This PMOS transistors separate's the storage node and writing node of data. They also scales the bit line voltage and prevents the flipping of contents in cell at low voltages. So stability parameters like SINM, SVNM, WTI and WTV also increased by 91%, 47%, 85% and 53% respectively. This all values are when compared with Sub-threshold 10T SRAM cell. This proposed circuit is also tested by giving 0.3 V power supply. Cadence Virtuoso tools are used for simulation with gpdk-90nm CMOS process technology.