Design and implementation of low power SRAM structure using nanometer scale

This paper investigates the design methodologies of Static Random Access Memory (SRAM) for low power consumption. The main aim of low power dissipation in the SRAM is to reduce the signal swings on the capacitive nodes like data lines and bit lines. The comparison of different SRAM structure on the basis of parameters like power dissipation with the variation of capacitor, temperature and supply voltages. The 16 bit memory has been designed. The technology used to execute the SRAM 6T, 8T and 11T is 350nm technology and the software used is TANNER TOOL.