FPGA-based level-shift PWM for an asymmetric multilevel trinary inverter

This paper deals with the design and development of conventional Level-shifted PWM techniques in a field programmable gate array (FPGA) for asymmetrical converters in a Trinary Hybrid Multilevel Inverter topology. Each modulation technique has been implemented in FPGA through a 32-bit single precision floating point architecture in accordance to IEEE-754 standard. Portability to other devices is ensured using VHDL. Embedded Block RAMs minimize FPGA resource usage, saving general logic resources, increasing overall speed and reducing power consumption. A comparison is presented in terms of resource consumption. An Asymmetric Cascaded Multilevel Inverter of single-phase nine-level is developed using Nexys 2 FPGA Card Board with Spartan-3E 1200. Experimental results are based on a two H-Bridged hardware prototype.