III–V MOS device technologies for advanced CMOS and tunneling FET

CMOS and tunneling-FETs (TFETs) utilizing high mobility III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport and tunneling properties. We addressed key issues to enhance the performance of III-V MOSFETs and TFETs. For the technologies enhancing the performance of III-V n-MOSFETs, InGaAs/InAs/InGaAs-OI QW channels combined with Tri-gate structures have been introduced. A fabrication technique of the InGaAs ultrathin body channels on large size Si wafers has also been demonstrated. Also, the effectiveness of III-V materials on TFETs through the enhancement of tunneling probability has been demonstrated. The superior InGaAs p⁺/n junction formation using Zn diffusion have provided better the TFET properties.