Vertical III–V nanowire transistors and CMOS circuits on Si

Summary form only given. III-V integration on Si is one of the most attractive options to extend future CMOS circuits. However, direct material integration by epitaxial growth is challenging mainly due to the large lattice mismatch. Here we present a novel technique that enables InAs and GaSb nanowires to be grown on Si substrates in the same MOVPE run. By reducing the Au seed size, the nucleation of GaSb can be suppressed resulting in InAs-GaSb as well as InAs nanowires. Vertical p and n-type MOSFETs, inverters and NAND gates have been fabricated and electrically characterized demonstrating the suitability of our method for large scale III-V MOSFET circuits on Si.