A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements

This paper proposes a simple digital automatic calibration method for wide-band continuous-time (CT) MASH ΣΔ ADCs. The main contribution of this method is the calibration of the errors due to the limited DC gain and 2nd pole of the loop filter integrators. The digital noise cancellation filters are calibrated by successive estimation of the DC gains and the 2nd pole, and updating the coefficients of the FIR filters. Extensive system-level and transistor-level simulations demonstrate the effectiveness and robustness of the proposed method. For an exemplary MASH ΣΔ ADC with BW of 600 MHz and SQNR of 75 dB, it can relax the DC gain requirement by 15 dB, and the 2nd pole requirement by three time, making it an enabling technique for power-efficient GHz-range ΣΔ ADC applications.