Advanced nanometer technology analog layout retargeting for lithography friendly design

In this paper a yield-aware template-based analog layout retargeting methodology for lithography-friendly nanometer technology designs is proposed. The yield performance is evaluated by probability of failure (POF), which is independent of any specific defect size, and is improved by wire-widening and wire-shifting inside the retargeting process. The non-traditional design rules, which are becoming prominent in the advanced nanometer technologies, have been tackled in the template. The retargeting flow is demonstrated from 0.18um CMOS technology to 65nm CMOS technology with significant yield improvement.