Evaluation of multi-level buck converters for low-power applications

This work investigates power losses in conventional and multi-level buck converters. Conduction and switching losses are modeled for conventional, 3-level and 5-level buck converters as a function of technology parameters, design variables and the operating point. It is shown that for a given set of technology parameters and optimized design variables, multi-level buck converters achieve higher efficiencies than the conventional buck converter at low output voltages and load currents. This shows that multi-level buck converters are more suitable for low power applications than the conventional buck converter. In addition, for low inductor quality factor (QF), multi-level buck converters achieve higher efficiencies than the conventional buck converter which makes them better suited for on-chip integration. The 65nm CMOS technology is employed. All models are validated against Spice simulations.