Pin assignment optimization for large-scale BGA packages using simulated annealing

In this paper, a package P/G pins assignment optimization method based on simulated annealing (SA) is proposed. Two objective functions describing power integrity (PI) and signal integrity (SI) are introduced. The basic flow of SA is presented, with the redefinition of the neighborhood of solution in SA, which ensures the feasibility in iteration. A 49×49 pinout example generated by the proposed SA method is presented, the compression of the SA example and the product from Xilinx is provided. By using this SA method, the P/G pins assignment of a large-scale BGA package with blocks of core, inputs/outputs and differential pairs can be generated in a few minutes automatically.