A wafer-level characterization method of ESD protection circuits for both component-level and system-level applications

Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer-level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly captured by the proposed method. Besides, both the component-level triggering criteria and system-level transient-induced latch-up (TLU) immunity of ESD protection circuits can be fully characterized by the proposed method. Silicon-data based case studies are presented in this work to verify the validity of the proposed method.