A model for the jitter of the clock path under external electromagnetic interference

The paper presents a time-domain model for the jitter of the clock path due to external electromagnetic interference on the power supply. A programming algorithm based on the model is raised to calculate numerically the value of the jitter. Transistor-level HSPICE simulations are executed on clock paths of various lengths. The clock gate is inverter of SMIC 130 nm, 1.2 V technology. Relationship between the jitter and interference frequency from 10 MHz to 10 GHz are simulated at fixed amplitudes. Relationship between the jitter and interference amplitude from 0V to 0.5V are simulated at fixed frequencies. Good agreement between the HSPICE simulation and Matlab calculation is observed over a wide range of interference frequency. Interesting phenomenon such as the jitter-minimum-shift and the jitter-snapback in simulations can be well explained and precisely predicted using the jitter model. The model requires only simple information from the gate circuit for jitter calculation. It could be developed into an EDA tool for predicting the clock jitter.