Design of 9-transistor content addressable memory cells using Schottky-barrier carbon nanotube field effect transistors

The work in this paper proposes a novel design and performance analysis of high performance content addressable memory (CAM) cell using Double gate (DG) Schottky-barrier carbon nanotube field effect transistor (SBCNTFET). The standard 9-Transistor model of CAM cell is implemented using circuit compatible model of DG SBCNTFET and simulated extensively using Cadence Spectre simulator. It has been found that DG SBCNTFET-based CAM cell can achieve 148.57× less power-delay-product (PDP) for read operation and 925× less PDP for write operation compared to CMOS based design. For search operation the PDP is 324× less in CNTFET-based CAM as compared to CMOS CAM cell. It has been also compared with the MOSFET-like CNTFET based 9T-CAM cell and it is found that it can achieve 36.84× less power-delay-product (PDP) for read operation and 44.8× less PDP for write operation and 52.46× less PDP for search operation.