A novel power efficient N-MOS based 1-bit full adder

A full adder circuit is considered as one of the basic building blocks of Digital Signal Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated Circuits (ASICs) and many other digital circuits and systems. Today, efficient full adder circuit design is one of the main challenges for VLSI engineers. This paper proposes a novel 1-bit full adder circuit designed using N-MOS based pass transistors logic. This proposed full adder has been simulated using 0.35um CMOS process technology at 2.5V supply voltage with ISIM and also with DSCH 2.6c simulator. The results of the post layout simulation (using MICROWIND 2.6a) have been compared with the results of similar previously reported adder circuits. The result analysis shows that the proposed adder circuit is highly efficient in terms of power, delay and area consumption, compared to many other full adder circuits.