High-level performance estimation of image processing design using FPGA

We propose a methodology for an early performance estimation of FPGA-based image processing applications. Using UML activity diagram of an application, each operator is decomposed into operational units with fine to medium granularity. Elementary operations are modeled experimentally in terms of latency, power and area to form a pre-characterized operators library. The results demonstrate that performance estimation at a very high abstraction level is already possible with an error less than 5%, and that the estimations are highly correlated to the results obtained in the final implementation.