A floating high-voltage level-shifter with high area efficiency for biomedical implants

A major problem in State-of-the-Art digital, floating level-shifters is, that they either require a large area when employing positive feedback, or lack accuracy with respect to the floating digital supply, if an open-loop solution is used. In order to reach accurate, floating, digital supply levels, while using the area efficient, static level-shifter topology, a control-loop for the reference current is introduced. Thereby process, temperature and time related variations are compensated and the adaptive reference can be distributed to an arbitrarily large array of level-shifters. The whole architecture has been simulated, layouted and manufactured in a standard 0.18 μm HV CMOS process. Simulation results show, that the design is capable of shifting digital signals from 0/3V to a floating 6/9V and -6/-9V domain with a delay of 250 ns and 150 ns respectively. By reducing the amount of high voltage transistors and utilizing low voltage diodes in the floating voltage domain, an area of only 65 μm × 33 μm per level-shifter can be realized. This is especially advantageous for the intended application in a multichannel neural stimulator, where many level-shifters are needed to switch the dedicated functions in the floating high voltage domains. The required bias current control-loop has a simulated power consumption of only 94 μW and requires an area of 137 μm × 97 μm.