Practices in High-Speed IO testing

With advances in VLSI technology, process, packaging, and architecture, SoC dies continue to increase in complexity. These advances have resulted in an unprecedented rise in design marginalities, manufacturing flaws and customer returns in SoCs with High-Speed IO circuits. This situation presents a challenge to develop sophisticated but low-cost test solutions. DFT-based test methods offer solutions to this challenge. This tutorial paper provides a summary of industry practices in DFT-based approaches to testing High-Speed IOs and their comparison with the specification-based tests.