High-speed decompression architecture of compressed HTTP streams for the internet routers

In recent years, studies of DPI have been carried out actively. HTTP packets, which are a kind of DPI target, include GZIP compressed packets, and multi-streamed GZIP compressed HTTP cannot be analyzed directly on routers. Moreover, wire-rate processing is required to achieve on-router analysis. In this paper, HTTP decompressing architecture on routers supporting 40Gbps network is considered, and three mechanisms, which are parallelized architecture, cache architecture and piggy-back method, were proposed for achieving higher throughput. Hardware cost simulations by using Verilog HDL confirms it can achieve 10Gbps throughput at low circuit costs.