Mechanistic relationship between instruction fetch width and basic block size to architectural vulnerability factor

Modeling and analyzing architectural vulnerability factor (AVF) of microprocessors is helpful in reliability-aware microarchitecture design. This paper derives formulas for computing AVF of critical pipeline structures by calculating the instruction occupancy of a structure based on instruction-level parallelism. A mechanistic relationship is shown to exist between instruction fetch width and basic block size to AVF. There is an upper bound threshold impact of variable fetch width and basic block size on AVF, and the value of this threshold can be calculated. There is a quadratic relationship for AVF from the minimum value between fetch width and basic block size. Experimental results prove the above conclusion. Based on this mechanistic relationship, a design architect can rapidly evaluate reliability, choose corresponding parameters at an early design stage, and obtain a better trade-off between reliability, performance, and cost.