General purpose FIR filter arrays using optimized redundancy over direct product polynomial rings

This paper presents architectures for implementing general purpose FIR arrays, using enhanced Fermat ALU theory. The structure is based on a direct product finite polynomial ring mapping of a redundant binary representation of the input data; in effect we exploit a double redundancy of the input representation and the mapped polynomial representation. By exploiting this redundancy, with attendant reductions in coefficient growth due to the polynomial multiplication, we are able to considerably reduce the probability of overflow error. The direct product computational channels all operate over the single Fermat prime, 257, and the silicon area overhead for the input/output mappings is less than 10%. This a considerable reduction compared to conventional and previous RNS designs of inner product processor array for DSP applications. We present results of test chips and 53 tap filter array designs using both a 0.5 micron and 0.35 micron CMOS technology. Power reduction estimates over equivalent binary implementations are at least 50%.