Pre-scalar for Diode Free Adiabatic Logic family

The appetency for high performance electronic devices in today's time imposes constraints on designers to make low power circuits. Various circuit styles and techniques are adopted to fulfill the aim. Adiabatic logic style is one of the most preferred logic styles for achieving high energy efficiency in the circuits. In this paper, the use of adiabatic logic style in the implementation of pre-scalars is demonstrated. The Diode Free Adiabatic Logic (DFAL) family has been chosen for the realization. The DFAL based divide-by-3 and divide-by-5 pre-scalars circuit maintaining 50% duty cycle are proposed. The functionality of the circuits is verified through TSPICE simulations by using 180nm CMOS technology parameters. Their performance is compared with the CMOS counterparts corroborating with the superiority of DFAL pre-scalars over CMOS logic in terms of power dissipation and power delay product.