An asymmetrical multilevel inverter topology with reduced source count

In this paper, an asymmetrical topology for cascaded multilevel inverter based on basic converter unit, series unit and full-bridge is proposed. It offers lower total harmonic distortion, switching losses and voltage stress on switches than conventional inverters. An algorithm to determine dc voltage sources magnitudes is proposed. The gating signals for the power switches are generated by employing Nearest Level Control (NLC) method. This structure allows a reduction of the system cost and size. Effectiveness of the proposed topology has been demonstrated by analysis and simulation.