Performance investigation of 32nm hybrid current conveyor

Moore's law has been an important benchmark for developments in the field of microelectronics and information processing in the last four decades. However there is a need to explore circuit designs in the newly emerging technologies to help extend the saturating Moore's Law. This paper investigates performance analysis of Current Conveyor with the hybrid (utilizing CMOS and CNFET technologies) approach at 32nm technology node. Current Bandwidth, Input and Output Port resistances of the device along with the average power dissipated are chosen as the parameters of reference for carrying out the analysis. Extensive simulations have been carried out using HSPICE simulator at a reduced power supply of ±0.9V.