FPGA based design and implementation of Reed-Solomon encoder & decoder for error detection and correction

This paper addresses to design an R-S (Reed-Solomon) encoder and R-S decoder and verify its functionality on FPGA. An RTL (register transfer logic) code was developed for an R-S encoder that takes a 32-bit input data and produces a 48-bit output. The logic synthesis and optimization of the code was carried out using Quartus II tool. Also, an R-S decoder was developed that decodes the transmitted data.