Low-power VLSI techniques for applications in embedded computing

Power dissipation is an important factor in the design of CMOS VLSI circuits for battery and externally powered applications in embedded computing. This paper presents an overview of a set of techniques that are suitable for CMOS technology and are readily usable by the VLSI system and circuit designer Supply-voltage-scaled CMOS is presented as a low-power approach for digital logic which offers a wide range of design points for trading off energy (and power) for circuit speed. Circuit and architecture techniques are presented which were originally developed for high performance, to sustain performance levels when the supply voltage is reduced. Finally, reduced-swing signalling, clock-powered logic, and stepwise charging are presented as techniques that can outperform supply-voltage-scaled CMOS for important design problems such as energy-efficient signalling.