A 14-bit 2.5-GS/s DAC using CAL-TRZ

A 14-bit 2.5-GS/s current-steering digital-to-analog converter (DAC) was designed in a 55-nm CMOS technology. For such a high sampling rate, time-relaxed interleaving digital random return-to-zero (TRI-DRRZ) is an effective method to improve the dynamic performance of the DAC by randomizing the switch glitches. A useful technique called CAL-TRZ is proposed in this paper. It combines TRI-DRRZ with a digital calibration operation. The digital calibration is used to ensure the static linearity of the DAC and further improve dynamic performance with small-size current source transistors. The pre-layout simulation shows that the proposed DAC achieves a spurious-free dynamic range (SFDR) >78 dB over 1250 MHz Nyquist bandwidth with a preset 0.5% mismatch of most significant bits (MSB) current sources.