The multiport CMOS memory cell based on the DICE trigger with two spaced transistor groups for hardened 65-nm CMOS SRAM

Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event transient, but not a single-event upset. The use of the new two groups DICE trigger with the spacing between the two groups more than 3 μm increases the soft-error immunity of the 65-nm multiport CMOS memory. In the address decoders, in registers of data and control of a multiport SRAM to improve immunity to the effects of single nuclear particles were used DICE flip-flops and combinational logic based on two-phase logic elements mutually spaced pairs of sensitive transistors on a chip. With these elements it was provided the minimum increase in the area as hardened multiport 65-nm CMOS memory cells, and the multiport SRAM while using guard rings and ohmic contacts compared with multiport cells and RAM on normal CMOS D-triggers.