Throughput evaluation model for the linear platform in semiconductor manufacturing

Equipment productivity in semiconductor manufacturing has been becoming one of the major topics due to the high equipment price. To calculate the productivity based on the running logs is easier and more precise. However, the engineers may often be assigned to estimate the productivity of the equipment in the design phase for making the investment decision or predicting the project benefit. In such a situation, no running log can be used to calculate the equipment productivity. If the architecture of the equipment and the wafer flow are simple, the equipment productivity still can be evaluated by some algebra-based solutions. Unfortunately, with the rapid IC shrink, the equipment architecture becomes more and more complicated. The linear platform is the typical one. In a linear platform, multiple main-frames are used to install more chambers. In each main-frame, there may be multiple robots for the efficient wafer transmission. It is very difficult to estimate the productivity of the linear platform by some simple algebra-based solutions. However, how to evaluate the accurate productivity of a linear platform is very critical due to its higher price. Aiming at this problem, a novel estimative methodology is proposed in this paper, which analyzes the potential waiting time of a chamber and then points out the productivity bottleneck of the platform. The proposed methodology is designed for calculating the Wafer Per hour (WPH) of the linear platform. The accuracy of the proposed methodology is verified by a simulation model. By applying the methodology, for a semiconductor manufacturing company, the incorrect equipment investment can be reduced to enhance the market competitiveness.