System Level Modeling of Timing Margin Loss Due to Dynamic Supply Noise for High-Speed Clock Forwarding Interface

Supply noise is conventionally modeled as a fixed voltage noise specification. Modern integrated circuit design cannot meet a conventional fixed voltage noise specification due to large dynamic noise. These days, applications of multicore system-on-chip (SoC) and multichip system-in-package become very common. The impact of dynamic noise can be even more detrimental for multicore or SoC design as supply noise can be completely uncorrelated between two regions whose powers are different. Accurate modeling of noise impact requires a new approach that can account for any jitter tracking in clock forwarding systems. In this paper, a comprehensive dynamic noise modeling methodology is presented to analyze jitter impact in various clock forwarding interfaces for multicore and SoC designs. The proposed method uses the frequency-dependent jitter sensitivity function with a noise spectrum to model the desired jitter tracking.