Design and implementation of FPGA based Digital Pulse Compression via fast convolution using FFT-OS method

Digital Pulse Compression (DPC) is one of the key steps in the signal processing of a radar system. It provides range resolution of the radar system as well as Signal to Noise Ratio (SNR) improvement of the received signal. To get higher SNR improvement by DPC, higher number of phase coded samples in the transmit pulse are required. Traditionally, it is implemented by Finite Impulse Response (FIR) filtering method. This leads to large number of taps (multipliers) of FIR filter, thus limiting the number of samples in the transmit pulse. With the advancement of technology, hardware implementation of higher number of FFT point operation is possible and hence fast convolution is preferred solution for DPC implementation. But, for high unambiguous range radars, large number of samples in the receive window leads to larger numbers of Fast Fourier Transform (FFT) points, thus, consumeing a huge portion of FPGA resources. This paper presents the approach of implementing Digital Pulse Compression via Fast Convolution using FFT — Overlap Save method (FFT-OS). This method will allow us to increase the number of samples in the receive window as well as reduce the length of FFT points to perform fast convolution.