A variable-latency, ultra-low-voltage RISC processor with a new in-situ error detection and correction technique

To overcome significant PVT variation in ultra-low-voltage (ULV) operation, a new in-situ error detection and recovery mechanism is proposed to optimize circuit design for typical-case. The proposed technique detects glitch of a (ctitical-path) circuit output within the setup-time duration of a flip-flop and stalls the clock source, if possible, until the output is stable once an error is detected. Applying the proposed in-situ error detection, a test chip of an ULV 32-bit simple RISC with a 128-point FFT has been implemented with TSMC 40 nm CMOS process. The chip's measurement results confirms the functional correctness of the proposed in-situ error detection mechanism. Comparing that with the simple RISC with conventional worst-case design principle, the proposed variable-latency ULV one reduces approximately 46% energy dissipation. And, with the similar energy consumption, the proposed ULV RISC achieves approximately 1.16 times throughput improvement.