High performance VLSI architecture for 3-D discrete wavelet transform

This paper presents a high-speed memory efficient VLSI architecture for three dimensional (3-D) discrete wavelet transform. A major strength of the proposed architecture lies in reducing the number and period of clock cycles for the computation of wavelet transform. This five stage pipelined architecture shares the partial load of the next stage with the present stage to reduce computational load at the next stage and critical path delay (CPD). The proposed architecture has replaced the multiplications by optimized shift and add operations to reduce the CPD. Implementation results show that the proposed architecture benefits from the features of reduced memory, low power consumption, low latency, and high throughput over several existing designs.