A 1V 800MHz 140Kb register file compiler using variation aware self-timing in 40nm bulk CMOS

SRAM memory compiler uses conventional replica bit-line based self-timing architecture, which uses logic cells to replicate bit-cell current to discharge replica bit-line. To achieve robustness & yield in our memory design, the replica circuit is over-designed (by calculating Read Margin Tuning(RMT) code in logic cells) to meet the worst case margin criterion, i.e. array bit-cell is in SlowNSlowP (SS) and tracking path is in FastNFastP (FF) corner (SS_FF). However, with the same RMT, the access time (TCQ) degraded by 16% to 40% across the compiler range for SS_SS corner. Also the read power specs are calculated in FF_FF using the same tuning which results in 10% to 30% degradation. In this paper we propose a technique to achieve fine granular programming range across target access time with on chip process variation, using same number of programming bits, which uses a sub-threshold leakage based process sensor to detect on chip process variations and re-program the tracking circuit accordingly. This effectively mitigates extra delays in tracking paths due to process variation and results in robust as well as accurate memory tracking. We have integrated this technique seamlessly in SRAM compiler which take up to 5% extra area and achieve up to 30% improvement in TCQ degradation as well as 20% of the read power degradation compared to the conventional architecture.