A 128-kb 25% power reduced 1T high density ROM with 0.55 ns access time using low swing bitline edge sensing in 16nm FinFET technology

A read only memory (ROM) using novel high speed single-ended balanced sense amplifier using a capacitance divider based reference voltage generation is presented. The bit-lines in the proposed scheme are precharged to zero level to mitigate non-selected bit-cell leakage. During read-1 bit-line high level is created using a current source. Thus more number of bit-cells per bit-line are connected. However this increases the bit-line load and thereby increasing the bit-line rise time. The charging current source and self timing are designed to charge the bit-line to just a fraction of the voltage supply, limited only by the offset of the sense amplifier and variations in the reference voltage. A 128-kb 1T High Density read only memory (ROM) with 256 bit-cells per bit-line is implemented in 16 nm bulk FinFET process. The 128-kb ROM macro realizes a 0.55 ns read access time at 0.85 V, with an improvement of 20% in access time and 25% in dynamic power dissipation over conventional ROM macro using the single ended inverter sensing scheme. Silicon area overhead is just 5% as compared to conventional ROM macro.