A novel technique for interdependent trim code optimization

As integrated circuits become increasingly complex, the fabrication process renders them more marginal to specification parameters. Consequently, these circuits have to be tuned post fabrication to compensate for process marginality and thereby optimize their performance as well as to improve yields. This process of tuning is commonly termed as trimming, wherein the right set of digital trim codes is identified and used as a calibration setting by writing these codes into the hardware configuration registers. This paper addresses the problem of carrying out multi-variable trims involving two or more parameters, codes for which must be simultaneously searched and set, in order to attain the desired performance of the circuit. A novel low-cost hardware implementation of the Simplex minimization algorithm with speed-up improvements is described. This implementation is amenable for on-chip BIST (built-in self-test) and can also be directly implemented as part of the ATE (automatic test equipment) program. Experimental results are presented on two industrial circuits. Improvements in terms of trim code search time and attaining better performance are shown.