Foundry TSV enablement for 2.5D/3D chip stacking

This article consists of a collection of slides from the author's conference presentation on foundry TSV enablement for 2D/3D chip stacking. Some of the specific topics discussed include: logic design and networking infrustructures; memory stacking; examples of applications supported by this stacking methods; cost benefit analysis of three-dimensional integrated circuit investments; processing technologies; CMOS impact and evaluation; ecosystem work flows; and product reliability.