A constructive task mapping algorithm for hard real-time embedded NoCs

GA-based optimisation algorithms have been known to be efficient techniques for finding schedulable task mappings for a Networks-on-Chip (NoC) based hard real-time embedded system. The algorithms' adaptive features, for example the simultaneous configuration of multiple design parameters and the selection of trade-off between several fitness values, facilitate the exploration of a large design space through the population of task mapping. A large population provides better diversity among individuals and this effectively improves the potential in finding a schedulable task mapping. However, this advantage has its own drawback that causes the increasing number of evaluations. As a result, the algorithm needs substantial time to find the schedulable task mapping. In this paper, a new constructive task mapping algorithm is proposed to overcome the problem. Unlike the GA-based algorithms, which depend on a population size to conduct effective search, the new algorithm creates a task mapping in a constructive way based on specific design properties. By this approach the number of evaluations is reduced in a single run, and hence it needs less time to find the schedulable task mapping. Based on our finding with the mapping of realistic test bench, the new task mapping algorithm showed that it could find a schedulable task mapping as good as the well-established GA, but in less time than what was consumed by the latter algorithm. Further evaluation with the synthetic test benches showed that it can achieve our specified performance target.