Optimal design of a voltage regulator based resonant switched-capacitor converter IC

This paper details efficiency analysis and characteristics of a gyrator resonant switched-capacitor converter (GRSCC) operating as a voltage regulator. Following the efficiency analysis, this paper introduces an optimal size-efficiency design procedure for IC realization of the converter. In area-sensitive applications, the optimization method combined with the converter's benefits present an attractive approach for better power delivery concepts for point-of-load (PoL) applications. Based on the optimization principles detailed in this study, an on-chip bridge GRSCC topology has been implemented in 0.18μm 5V CMOS process. The analysis has been verified by post-layout analysis and measurements of the fabricated IC. Neglecting the package limitations, the prototype operation is demonstrated with 10 MHz switching frequency, up to 3A, 4.5 W with 3V input voltage, and the efficiency is measured to be 87%. The study has been extended to survey on effects of the package on the performance. The experimental measurements of the manufactured IC have been found to be in very good agreement with the theoretical analysis and optimization process, as well as to accurately estimate the package contribution to the system performance. In addition, a fully monolithic control system to regulate the output voltage is described and implemented on-chip by an automated synthesis process and place-and route tools.