Miniaturization of system in package for wearable devices using copper pillar solder flip chip interconnects

A small form system in package (SIP) is required to interface with multiple integrate circuit (ICs) of different functionality, passive components, and/or MEMS assembled into a single package that performs as a system or sub-system, this raise a great challenge to related either flip chip or wire bond interconnect technology in electronic packaging for high density, small feature size, and high performance. With technological development like thermal compression bonding (TCB), interconnects have been reduced to considerable fine pitch at below 25um bond pitch, but traditional diffusion bonding method likes Au-Au and Au-Sn bonding has a disadvantage of high cost and reduced throughput for multiple die package. Contrary to this Cu pillar solder reflow provides an excellent throughput at reasonably low cost, but they do have pitch limitations which is normally greater than 100 μm. This paper is targeted at resolving these challenges to exploit the advantages of Cu pillar reflow technologies and prepare a low cost solution for fabricating SIP, which requires for multiple die and fine pitch interconnects. Study was done on flexible substrate made of 25 μm polyimide tape with different layer count up to 4 metal layers. The Cu pillar bump pitch was kept at 80 μm with Cu pillar height of 10-13μm and solder cap height of 12-15μm (low profile type). Variations in substrate surface finish, pad sizes, substrate flatness were investigated thoroughly. In final, the substrate flatness is identified to be the primary contributor to prevent open solder failure, the OSP is found to be the most suitable candidate to ensure good solder joint integrity, and this offers a solution for developing SIP and provides an insight to designer for consideration of upcoming wearable electronics devices.