The alignment performance study for the gate layer in FinFet processes

As the shrinking of chip size continues, the demand for the improvement of the total lithographic overlay performance in the semiconductor industry become increasingly higher, which has resulted in proportionally higher requirement on the alignment performance. When the semiconductor processes reaches the 1X generation, and when the FinFet device becomes a mainstream technology, the lithographic process becomes more complex, which requires multiple patterning with the self-aligned spacer process, or self-aligned double patterning (SADP). The self-aligned process utilizes spacer over-etch to accomplish the pitch division, which can completely change the original micrometer size alignment marks to small bumps around a few tens of nanometers. This will drastically reduce the signal level of alignment detection. Even worse than this, when the upper layer needs a deposition of opaque layers, such as polycrystalline silicon, or some hard masks, the signal can be extremely weak. In this paper, we mainly focused our study on the alignment quality of the layer on the top of a sample SADP layer. We have studied the impact of some opaque thin film to the alignment signal. And we will compare the signal strength, or the ASML wafer quality (WQ), of different alignment mark design, such as, AH32, AH53 and AH74. Finally, the WQ improvement study and overlay results will be also discussed in the paper.