Simulating wafer bow for integrated capacitors using a multiscale approach

To simulate the bow of wafers with integrated capacitors in the form of pit arrays, various approaches were pursued. After unfruitful attempts to reliably obtain the wafer bow directly from simulating part of the wafer, a multi-scale approach was used. In this approach, the layer with the integrated capacitors was replaced by a homogeneous material having the same properties. Small-scale simulations of representative parts of the layer were performed to determine its effective stiffness tensor. Inclusion of the intrinsic strains of the grown and deposited dielectric and conductive layers enabled the volume change to be calculated of the layer with the integrated capacitors upon fabrication. Finally, the structure obtained was used in a full-wafer-scale model to simulate the bow of the wafers. Even for uncalibrated values for the coefficients of thermal expansion, most simulations agreed well with measurements.