Low power high-speed 10 Gb/s 4∶1 multiplexer for sliding-IF digital centric transmitter in 65nm CMOS

This paper presents a high speed 4:1 multiplexer (MUX) which can operate up to 10 Gb/s. The circuit adopts a simple transmission gate (TG) structure for low power consumption and saving area as well. It is dedicated to be employed into a sliding-IF transmitter architecture and acts as a digital multiplier in order to convert I/Q baseband data into a digital serial data stream before being up-converted into the analog domain through a radio-frequency digital-to-analog-converter (RF-DAC). In order to avoid glitches due to clock desynchronization, a 4-bit selectable delay-cell array is used for proper alignment configuration. The simulation results after post-layout extraction show a power consumption less than 5 mW under a 1.2 V supply voltage. The circuit has been designed in 65nm TSMC CMOS technology.