Ultra Low-Voltage static precharge NAND/NOR gates

The Ultra Low-Voltage (ULV) NAND and NOR gates are presented in this paper. These gates are based on the ULV precharge inverter presented in [11]. We intend to verify the gates' logical expression of NAND and NOR. The inbound precharge logical behaviours of the gate have been previously discussed, and therefore we aim to compare these new NAND and NOR designs to traditional Domino and CMOS logic styles. This paper focuses on the aspect of delay. All results are obtained by simulation in Cadence for a 90 nm TSMC fabrication process.