A proposal for the concept of pore-engineering as a method for controlling memory characteristics of resistive switching memories

A `pore engineering', which is an innovative method for controlling the memory performance of conducting-bridge random access memory (CB-RAM) by regarding the polycrystalline oxide memory layer as a nano-porous body, is proposed. This method is intended to control resistive switching properties by controlling the size of the pores, physical and chemical properties of the pore surface, and by providing an appropriate solvent to the pores. In this paper, a forming, set, and reset voltages, and reset current as well as their dispersions were confirmed to be decreased by providing appropriate solvents for the enhancement of electrochemical diffusion of Cu ions to the polycrystalline HfO₂ layer of Cu/HfO₂/Pt structures.