Protection of memory using code redundancies a survey

The issue of soft errors is an important emerging concern in the design and implementation of microprocessors. It is necessary to protect memory cells using Error Detection and error correction (ECC) codes such as hamming codes, Parity Matrix codes, Reed-Solomon codes, Punctured difference set (PDS) codes, LDPC codes and so on. The main problem is that they require complex architecture, higher delay overhead and more redundant bits. In this paper, a survey of such codes and their issues are presented. This paper is based on Decimal matrix code (DMC) with Encoder Reuse Technique (ERT) used to minimize area overhead.