Electrostatic discharge (ESD) technology benchmarking strategy for evaluating ESD robustness of CMOS technologies

This paper describes an ESD technology benchmarking strategy for evaluating the ESD robustness of a semiconductor technology. The strategy consists of a set of CMOS "building block" test structures, a matrix of these test structures, electrical characterization parameters, ESD metrics, a standardized failure criteria, and an extraction and testing procedure.