Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

The SOCs produced nowadays provide a high level of functionality, serve a wide range of applications, while becoming more efficient and cost effective. The complexity of the SOCs is also reaching its peak level. Around 10 to 12 numbers of analog IPs and digital IPs blocks are incorporated into the single SOC. It also supports multiple voltage domains that often simultaneously a combination of internal and external regulation modes. For modern age embedded systems to operate with high range of power and performance, the system must be power aware but not just consume low power. This paper presents the design detail of embedded RISC processor with dynamic power management capability. In this paper, we implemented a RISC processor with power management that keeps on tracking access to I/O devices while processing and power aware techniques within coding that lower the power consumption of system. Paper describes about the proposed system architecture, synthesis and simulation results analysis of the design. The coding is done with verilog-HDL and these coded designs are synthesized and simulated using Xilinx ISE 12.3 (Xilinx ISim simulator) and power calculation is done using Xilinx Xpower analyzer.