2.4 GHz CMOS digitally programmable power amplifier for power back-off operation

This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP
_1dB
), saturated output power (P
_SAT
) and power gain at 2.4 GHz. The lowest power mode achieves an 8.1 dBm P
_SAT
, a 13.5 dB power gain and consumes 171 mW DC power (P
_DC
) at an OCP
_MB
of 6 dBm, whereas the highest power mode reaches an 18.9 dBm P
_SAT
and a 21.1 dB power gain and consumes 415 mW P
_DC
at an OCPmb of 18.2 dBm.